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A novel hardware architecture is presented for the Algebraic Codebook Search function wed in GSM Adaptive Multi-Rate speech encoding. This architecture was for a System-on-Chip GSM baseband processing platform and is an accelerator for use with a programmable DSP Intellectual Property Core. Features of the algorithm are exploited to achieve an efficient hardware-software partitioning. The over all effect is a 5x reduction in power consumption and a 28% reduction in MIPS.

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