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This paper presents a CMOS amplifier-multiplier-antenna array capable of generating an EIRP of 3-4 dBm at 420 GHz. The chip is built using a 45-nm CMOS SOI process, and efficient on-chip antennas are used to extract the power out of the chip. The design is based on a 90-110 GHz distribution network with splitters and amplifiers, and a balanced quadrupler capable of delivering up 100 W of power at 370-430 GHz. The amplifier-multiplier concept is proven on a 2 4 array, and it can be also scaled to any array using additional W-band splitters and amplifiers.