Short, medium, and long on-chip interconnections having linewidths of 0.45-52 m are analyzed in a five-metallayer structure. We study capacitive coupling for short lines, inductive coupling for medium-length lines, inductance and resistance of the current return path in the power buses, and line resistive losses for the global wiring. Design guidelines and technology changes are proposed to achieve minimum delay and contain crosstalk for local and global wiring. Conditional expressions are given to determine when transmission-line effects are important for accurate delay and crosstalk prediction.

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In this paper, the self-consistent, frequency-dependent dielectric constant ( ) and dielectric loss tan ( ) of several materials are determined over the range 2 to 30 GHz using a short-pulse propagation technique and an iterative extraction based on a rational function expansion. The simple measurement technique is performed in the time domain on representative printed circuit board wiring. Broadband, fully causal transmission-line models based on these results are generated up to 50 GHz for card wiring using low loss materials including BT, Nelco N4000-13, and Nelco N4000-13SI. Simulation and modeling results highlight the need for the accurate frequency-dependent dielectric loss extraction. Signal propagation based on these results shows very good agreement with measured step and pulse time-domain excitations and provides validation of the measurement and model generation technique.Index Terms-Dielectric loss extraction, lossy causal transmission-line models, printed circuit board characterization, short-pulse propagation measurement technique.