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This paper discusses extensions to Verilog-A that address compact modeling needs. It reviews compact modeling and analog circuit simulation, and then presents a simple Verilog-A compact model for a capacitor. Based on this example, extensions are presented that make Verilog-A better suited to compact modeling. A tentative implementation of each extension is proposed and described. The paper concludes with a summaly of the extensions, implemented in a revised capacitor model.