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This paper presents review on different pipelined FFT architectures and proposes a new pipelined FFT architecture with twin parallel processing after second stage. The proposed architecture follows a novel data flow path, Twiddle factor generation and multiplication is implemented by multiplier and shift registers. The first two stages are implemented by multipath pipelined form after that it follows twin parallel form. The twin parallel form consists of two pipelined units simultaneously generates FFT output values. This architecture reduces latency in a greater extent with a smaller cost of hardware. The proposed architecture compared with previous architectures. The proposed architecture is implemented for Radix-2 and Radix-22 DIF FFT. The throughput of proposed architecture is four.