This paper deals with The rapid progress in semiconductor technology have led the feature sizes of transistor to be shrunk there by evolution of Deep Sub-Micron (DSM) technology. There by the extremely complex functionality is enabled to be integrated on a single chip. So, transistor size is reduced to few nanometers. By reducing the size drastically some problems are occurred. In that leakage power is one of the disadvantage. By using this stacking technique we are going to reduce the leakage currents.