Low-temperature polycrystalline silicon thin film transistors (poly-Si TFTs) have been studied because of their high performance in Active Matrix Liquid Crystal Displays (AMLCD's) and Active Matrix Organic Light-Emitting Diode (AMOLED) applications. The purpose of this work is to simulate the impact of varying the electrical and physical parameters (the interface states, active layer's thickness and BBT model) in the transfer characteristics of poly-Si TFT to extract the electrical parameters like the threshold voltage, the mobility and to evaluate the device performance. The device was simulated using ATLAS software from Silvaco, the results show that the electrical and physical parameters of poly-Si TFT affect significantly its transfer characteristics, choosing suitable parameters improve high-performance transistor. Such results make the designed structure a promising element for large-scale electronics applications.    

Recently polycrystalline silicon (pc-Si) thin film transistors (TFT’s) have emerged as the devices of choice for many applications. The TFTs made of a thin un-doped polycrystalline silicon film deposited on a glass substrate by the Low Pressure Chemical Vapor Deposition technique LPCVD have limits in the technological process to the temperature < 600°C. The benefit of pc-Si is to make devices with large grain size. Unfortunately, according to the conditions during deposition, the pc-Si layers can consist of a random superposition of grains of different sizes, where grains boundaries parallels and perpendiculars appear. In this paper, the transfer characteristics IDS-VGS are simulated by solving a set of two-dimensional (2D) drift-diffusion equations together with the usual density of states (DOS: exponential band tails and Gaussian distribution of dangling bonds) localized at the grains boundaries. The impact of thickness of the active layer on the distribution of the electrostatic potential and the effect of density of intergranular traps states on the TFT’s transfer characteristics IDS-VGS have been also investigated.

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Recently polycrystalline silicon (pc-Si) thin film transistors (TFT's) have emerged as the devices of choice for many applications. The TFT's made of a thin un-doped polycrystalline silicon film deposited on a glass substrate by the Low Pressure Chemical Vapor Deposition technique LPCVD have limits in the technological process to the temperature < 600°C. The benefit of pc-Si is to make devices with large grain size. Unfortunately, according to the conditions during deposition, the pc-Si layers can consist of a random superposition of grains of different sizes, where grains boundaries parallels and perpendiculars appear. In this paper, the transfer characteristics I DS -V GS are simulated by solving a set of two-dimensional (2D) drift-diffusion equations together with the usual density of states (DOS: exponential band tails and Gaussian distribution of dangling bonds) localized at the grains boundaries. The impact of thickness of the active layer on the distribution of the electrostatic potential, the effect of density of intergranular traps states and grain size on the TFT's transfer characteristics I DS -V GS have been also investigated.