We present for the first time the full integration scheme and 512Mb product data for a trench DRAM technology targeting the 48nm node. The key technology enablers are a new cell architecture "Wordline over Bitline" (WOB)-realizing a high degree of self-alignment and small parasitic capacitances, together with high performance periphery C devices at reduced internal voltage, and the integration of a BS MIC/ HfSiO trench capacitor.

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