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As imaging is a process of 2D projection of a 3D scene, the depth information is lost at the time of image capture from conventional camera. This depth information can be inferred back from a set of visual cues present in the image. In this work, we present a model that combines two monocular depth cues namely Texture and Defocus. Depth is related to the spatial extent of the defocus blur by assuming that more an object is blurred, the farther it is from the camera. At first, we estimate the amount of defocus blur present at edge pixels of an image. This is referred as the Sparse Defocus map. Using the sparse defocus map we generate the full defocus map. However such defocus maps always contain hole regions and ambiguity in depth. To handle this problem an additional depth cue, in our case texture has been integrated to generate better defocus map. This integration mainly focuses on modifying the erroneous regions in defocus map by using the texture energy present at that region. The sparse defocus map is corrected using texture based rules. The hole regions, where there are no significant edges and texture are detected and corrected in sparse defocus map. We have used region wise propagation for better defocus map generation. The accuracy of full defocus map is increased with the region wise propagation.

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There is vast variation encountered in present circuits because of aggressive scaling and process imperfections. So this paper deals with various D flip-flop circuits in terms of robustness and propagation delay. This work compares various known D flip-flop circuits and then identifies the circuit which is fastest as compared to others taken into consideration. Further, delay variability exhibited by circuits has been analyzed to test the immunity against PVT variations i.e. process, voltage and temperature. In this paper, we have investigated the output levels of various D flip-flop circuits. Push-pull isolation D flip-flop proves to be more efficient as compared to other circuits in terms of delay variability. The circuits have been simulated using 32-nm technology node on SPICE. The designs offering minimum delay and its variability are reported, to aid the designer in selecting the best design depending on specific requirements.