No abstract

A 5.7 GHz low noise ultra high gain CMOS LNA with inter stage technique is presented in this paper. The noise and gain performance is improved using common-source transistor inter stage network. A bias resistor of large value is placed between source and the body node to prevent body effect and reduce noise. The simulated 0.18 μm CMOS LNA achieves −14 dB and −17.5 dB input and output return loss respectively. Compared to previously published currentreused LNA, the proposed LNA has the smallest noise figure of 1.85 dB, extremely high gain 32.5 dB, and the highest Figure of Merit of 87.28.

No abstract

No abstract

No abstract