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In this paper a new CMOS current-mode four-quadrant analog multiplier circuit is proposed. The major advantages of this design are high linearity, high speed and low power consumption. Removing dc offset is the most important improvement in this topology. The circuit is designed with 1.8V supply voltage and is simulated using HSPICE simulator by level 49 parameters in 0.18µm standard CMOS TSMC technology. The aspect ratios of the MOSFETs are optimized using Evolutionary algorithm by MATLAB. The simulation results of this analog multiplier demonstrate a maximum linearity error of 2.6%, a THD of 1.77%, maximum power consumption of 157 µW,-3dB bandwidth of 241MHz and almost free from dc offset.

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