N36-8the earth and interact near or within IceCube and produce a muon. The muon will continue in much the same direction through IceCube and produce Cherenkov light along a cone in the forward direction. Some of this light is recorded by the DOMs. From the ensemble of Hit information it is possible to reconstruct the direction of the neutrino via the muon tracks with a precision of about 1 degree. Upwardgoing neutrinos can be detected in this way even though downward-going cosmic ray muons exceed their rate by a factor of approximately 10 6 . Abstract-A "TrackEngine" (TE) concept has been developed for use with IceCube to maximize track-finding efficiency in the presence ofnoise. IceCube is a km-scale neutrino detector under construction at South Pole, now consisting of 40 strings of 60 Digital Optical modules (DOM) sensitive to Cherenkov light. Each DOM includes a large PMT that generates noise pulses at~500 Hz. The detection by a DOM ofa pulse, noise or signal, generates a "Hit". The full-scale IceCube will consist of 86 strings, and is expected to generate an average ofapproximately 13 random Hits during any 5f.Js window, the characteristic traversal time within the array ofa relativistic muon. Data is currently acquired with a simple multiplicity trigger (SMT) requiring at least 16 DOM Hits, with the additional requirement that these Hits form local coincidence pairs (8 Hit pairs). However, this trigger is inefficient, especially for low energy muons that generate a minimum oflight, but are of special interest for many experimental studies such as detecting signals from WIMP annihilation in the earth or sun. To increase efficiency for dim tracks, the TE examines all Hits, paired or not, and exploits topological features characteristic of straight line trajectories within the array to identify muons even in the presence ofsubstantial noise. A single PC and FPGA combination is expected to handle the full IceCube Hit rate of 2.5 MHz with more than a factor two margin. The received Hits are time sorted in a PC andfed to a Xi/inx ML507 FPGA board implementing the track engine algorithm. The FPGA solution was chosen, since it could be shown that the present algorithm cannot be implemented in software on one PC alone. The design reaches its high performance by an extensive pipelining of the calculations and operations, well designed and optimized network nodules in software and an extensive use ofthe fast, single-cycle delay Block RAM available in the FPGA.