Power-gate is a well-known technology used to decrease static (leakage) power consumption in low-power circuit currently. Several PMOS transistors are used as power switches (p-switches) to control the power source within the power-gating circuit. The p-switches are attached between the Vdd and the virtual Vdd power rail which served as the power source of circuit. The system of power management unit will turn off the power supply of the idle core by switching off the p-switches. As we know, the performance of a circuit depends on whether the supplied current is sufficient or not, and it relies on how much the channel width of p-switches could turn on simultaneously. Some defects will make the p-switches channel width diminished. The phenomenon of reducing channel width will not only affect the circuit performance but also cause chip reliability degrades because the current flow

A low power voltage management technique is proposed to reduce power consumption for domino circuits. Exploiting a rising and charge-sharing voltage allow the domino circuits to have both high performance and low power consumption. A test chip has been successfully validated to achieve 68% dynamic power consumption and 15% static power consumption respectively using TSMC 0.13um CMOS technology.

The first dual mode video decoder with 4-level temporal/spatial scalability and 32/64-bit adjustable memory bus width is proposed. A design automation environment of simulation and verification is established to automatically verify the correctness and completeness of the proposed design. Using a 0.13 μm CMOS technology, it comprises 439Kgates/10.9KB SRAM and consumes 2~328mW in decoding CIF~HD1080 videos at 3.75~30fps when operating at 1~150MHz, respectively.