The most efficient combo/driver solution in terms of cost and performance is SoC. In this paper, a single chip with both CD/DVD decoding and CD-R/RW recording functions is proposed for a COMBO driver application. The general system specification is 56/32/56/16, indicating CD-R recording speed up to 56XS, CD-RW recording speed up to 32XS, CD-ROM decoding speed up to 56XS, and DVD-ROM decoding speed up to 16XS. In addition, this COMBO SoC supports some dedicated functions including DVD-RAM decoding, Mt. Rainier CD-RW format, and the true constant angular velocity (CAV) recording mode. Except the robust controls of the servo system and the laser power, the mechanisms for rapid disk ID detection and automatic calibration are also provided in this approach. Figure 23.6.1 shows the COMBO SoC block diagram.The analog signal processor receives the analog RF and servo signals from the optical pickup unit (OPU). The S/H and matrix circuit as well as the servo and detection block generate various signals, such as focusing and tracking error signals, to precisely control the OPU position. Moreover, the differential phase detection (DPD) circuit is used for both track counting and following functions as DVD decoding. The wobble signal processing unit is implemented to extract the absolute time in pre-groove (ATIP) information from the CD-R or CD-RW disc. The analog signal processor also includes the automatic power control (APC) circuit with built-in D/A converters to ensure stabilized laser power for both CD and DVD systems. The RRF/ROPC block provides the optimal laser power for disc recording application. Note that the RF equalizer consists of a seven pole, two zero Gm-C filter and the tuning circuit is implemented to enhance the signal-to-noiseratio of the eight-to-fourteen modulation (EFM) signal. The cutoff frequency can be programmed from 3MHz to 70MHz and the gain boost is adjustable from 0dB to 11.4dB. Furthermore, the built-in band-gap voltage reference circuit provides 1.4V/2.0V/2.8V references. After receiving the data signal from the analog front-end processor, the channel data processor including a built-in data PLL is designed for the data demodulation.The digital part mainly contains the following modules: CD-ROM encoder/decoder, DVD decoder, servo DSP controller, audio processor, ATIP decoder, spindle motor controller, defect management module, interface controller, 8b µProcessor, write power control and write strategy timing generator. An optimal power control (OPC) calculator is also implemented with 0.1mW power resolution as well as a built-in jitter meter with 0.9ns resolution. The interface controller includes the buffer memory manager, the DMA interface microcontroller, the flash programming and the enhanced-IDE (ATAPI) host interface controller. Since several complicated arithmetic operations and macro functions such as ATIP decoding can be executed by hardware instead of firmware, only an enhanced 8b µP controller is utilized to achieve the realtime controlling mechanism. In contrast to other approach...