A novel design of a test pattern generator (TPG) for built-in self-testing (BIST) of path delay faults, is proposed. For a n n-input CUT, the TPG generates a sequence of length (n.2" +1), that includes all n.2" single-input-change (SIC) test pairs, and hence optimal. The generation of such a sequence of minimum length (i.e., n.2' + 1 ) was a n open problem. A simple iterative circuit of the TPG is then constructed. This provides minimum test application time for testing path delay faults, and compares favorably with the earlier BIST designs.