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In this work, we present the first integrated circuit implementation of our previously proposed dual entropy core TRNG architecture, which is designed following a novel parameter variation-aware approach. A prototype integrated circuit has been fabricated in 180nm CMOS technology. Prototype chip achieved 35Mbps throughput with approximately 33pJ/bit energy efficiency. Random numbers acquired from the prototype chip have successfully passed all NIST 800.22 statistical tests without requiring any post-processing.