The evolution of portable electronic devices and their widespread application has led to an increased focus on power dissipation as one of the critical parameters. An increase in functionality requirement and design complexity on a single chip has resulted in increased power dissipation. High power dissipation has motivated study and innovation on low power circuit design techniques. Adiabatic logic has been studied as one of the design techniques to reduce power dissipation by reusing the power that was getting dissipated in conventional designs. This paper presents the application of Wave Shaping Diode Adiabatic Logic (WSDAL) to implement an ALU and analyse the improvement in power dissipation as compared to the conventional CMOS design. The WSDAL design uses a slow and time-fluctuating 2-phase sinusoidal Power Clock (PC), which supplies power as well as a clock to the designs. WSDAL uses an Ultra-Low Power Diode (ULPD) structure that operates as a wave shaping device and reduces glitches at the output. The design has been implemented in OrCAD Capture and simulated using Pspice in TSMC 180nm technology. The simulations were performed at 200MHz PC frequency and power dissipation was studied over a range of voltages from 1.4V to 2.2V. The simulations show that WSDAL ALU dissipates less power than the CMOS design. This study indicates that WSDAL-based designs have the potential to be deployed for power dissipation reduction in portable devices.