In this paper a new computationally simple scheme is proposed for model order reduction to design a Lag-Lead compensator for higher order linear discrete systems. Artificial Bee Colony (ABC) algorithm is employed to obtain a successful reduced order model for an Original higher order discrete system via Bi-linear transformation. ABC algorithm is based on minimization of Integral Square Error (ISE) between Original and reduced order models pertaining to unit step input. A Lag-Lead compensator is designed for the reduced order model with desired performance specifications and the designed compensator is cascaded with the Original higher order model to improve the stability .

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