MCML (MOS Current Mode Logic) is a method used for the purpose of reducing the delay and power of the circuit. In high speed application this method is used to reduce the power. In this method the sleep transistor is inserted in series with the supply voltage (or) current source to reduce the power. Different power gating techniques are been used to reduce the static power and to improve the speed and efficiency of the circuit. In this paper, the filter can be designed by using MCML logic. The fourth order band pass filter by using MCML logic is introduced. In order to reduce the power and delay this method is proposed.

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MCML (MOS Current Mode Logic) is a method used for the purpose of reducing the delay and power of the circuit. In high speed application this method is used to reduce the power. In this method the sleep transistor is inserted in series with the supply voltage (or) current source to reduce the power. Different power gating techniques are been used to reduce the static power and to improve the speed and efficiency of the circuit. In this paper, the filter can be designed by using MCML logic. The fourth order band pass filter by using MCML logic is introduced. In order to reduce the power and delay this method is proposed.

Adders are of fundamental importance in a wide variety of digital systems. This paper presents a novel bit block structure which computes propagate signals as carry strength. Power consumption is one of the most significant parameters of carry select adder.The proposed method aims on GDI(Gate Diffusion Input) Technique. Modified GDI is a novel technique for low power digital circuits design further to reduce the swing degradation problem. This techniques allows reduction in power consumption, carry propagation delay and transistor count of the carry select adder.This technique can be used to reduce the number of transistors compared to conventional CSLA and made comparison with known conventional adders which gives that the usage of carry-strength signals allows high-speed adders to be realised at lower cost as well as consuming lower power than previous designs. Hence, this paper we are concentrating on the area level &we are reducing the power using modified GDI logic.