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This paper presents the rationale for νMOS-based realizations of digital circuits when logic design techniques based on threshold logic gates (TGs) are used. Some practical problems in the νMOS implementation of threshold gates have been identified and solved. The feasibility and versatility of the proposed technique as well as its potential as a low-cost design technique for CMOS technologies have been shown by experimental results from a multi-input Muller C-element. The proposed new realization exhibits better performance related to delay, area and power consumption than the traditional logic implementation.

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The sections in this article are Threshold and Majority Gates Threshold‐Gate Networks Application to Median and Stack Filters