PACS 82.45.VpIn this study, we have demonstrated the possibility of using macroporous silicon electrodes in electrochemical capacitors. Macroporous silicon was used to increase the surface exchange between pore surface and electrolyte. The inherent resistivity of the porous silicon can be reduced through the use of subsequent doping and metallization processes of the macropore surface. A systematic study of the electrolyte concentration and the porous silicon depth influences was also performed. A unit cell capacitance value of 320 µF/cm 2 was obtained with doped and metallized p-type macroporous silicon electrodes.

Porous silicon (PS) formed from low doped silicon is reported to be a promising material for power electronic applications for electrical insulating. However, post-anodization steps on porous silicon, such as photolithography or metallization require the implementation of smooth porous silicon surfaces. In the present work, we use low doped (30-50 Omegacm) p-type Si. Our experiments allowed us the implementation of structures with pore dimensions extending from some micrometers (macroporous PS) to few nanometers (microporous Si). The use of a particular solution based on HF-H2O and acetic acid permitted to achieve microporous Si structures. The evaluation of the porosity versus the thickness is found to be a pertinent parameter to study the structure integrity of the so formed microporous silicon. Thus, layers with a thickness up to 400 microm have been implemented with a porosity of 50%.

In this paper, we present processes to etch high thickness porous silicon layers for RF device applications. Indeed, on‐chip inductors realized on bulk silicon suffer from mediocre Q‐factor values mainly because of electrical losses into the substrate and capacitive coupling with the silicon appearing beyond 1 GHz. We present a detailed study of etching parameters such as the current density or the HF concentration in HF: H2O:acetic acid based electrolytes. In addition, we propose a prospective study of integrated copper inductor performances on porous silicon substrates in the range of 100 MHz to 10 GHz. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

A novel micro-machining technique for silicon deep anisotropic etching and isolating porous silicon structure formation is developed in this paper. This method combines aluminum thermomigration through a N type silicon wafer and silicon electrochemical etching in a HF-based solution. Using this technique, high aspect ratio trenches (1:5) and porous silicon isolating regions have been achieved through the entire thickness of the silicon wafers. Etch rate measurements have been performed varying the anodization current density. A maximum value of 22 µm.min -1 has been obtained. Moreover, the porosity behavior with the current density increase is also discussed.