Nine imagers that exploit distinctive CID properties and incorporate on-chip amplifier configurations (including preamplifier/pixel) were developed for use in automation, nuclear and scientific applications.TV compatible (1 1 mm) formats of 768H X 575'i (European) and 755H X 484V (domestic-RS17O) were fabricated for radiation-hardened product cameras. Operating CIDs provided excellent signal-to-noise at radiation levels of 106 rads/hr, and accumulated dose beyond 1 0 6 rads in silicon (60Co source).Large format imagers featuring random pixel and subarray addressability, were created for spectroscopy and other scientific applications. They possess a 27 X 27 .tm2 pixel in 1024H X 1024V, 1024H X 256V, and 512H X 512V formats. Pixels and subarrays (even overlapping subarrays) can be read out destructively or non-destructively. The above features can be combined with two-dimensional on-CID pixel binning because CID binning preserves the spatial fidelity of the pixel charge.Two 1024 linear-type imagers were fabricated with a preamplifier-per-pixel structure and a 27 X 150 im2 large capacity photo-site. One device features on-chip large signal differencing capability between successive exposures.Two 512H X 5l2V (20 X 20 .Lm2 pixel) format imagers were created for UV photon-counting applications. The imagers provide high local count rates through video-rate random subairay addressability and subarray charge injection. L INTRODUCTIONAdvances in integrated wafer processing technology are creating the opportunity to develop new solid state imaging devices that incorporate key attributes and overcome deficiencies of existing imaging array detectors. Sub-micron technology provides the means to create dense pixel arrays and circuitry, and embed low-noise preamplifiers, complex signal processors and pixel decoding functions peripherally on-chip or within a pixel. Placement of these functions on-chip is a natural evolutionary step for CIDs and will substantially embellish their proven versatility with dramatic improvements in low-noise performance.Charge injection (CD) and charge coupled (CCD) imaging device technology developed concurrently since the early 1970's. Both devices are charge transfer devices (CTDs) whereby signal charge is collected under MOS gates, then transferred and sensed as a voltage during the pixel readout process. Fundamental differences lie in their pixel readout structure and technique. CIDs possess versatile and unique readout capabilities that have established their utility in scientific, radiation and automated measurement applications. CCDs, with their inherently low readout noise structure, have demonstrated a low level video performance that has established their dominance in picture making applications.The two "cultures' appear to be merging into new forms of "preamplifier-per-pixel" (PPP) sensors, sometimes called active pixel sensors (APS), that seek to combine the versatility and robustness of the CID structure with the impressive low-noise performance of CCD structures. A significant step in ...

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I.AbstractThis paper describes a new improved method of employing an amplifier per pixel that eliminates VET threshold and gain variations problems of prior art. Existing amplifier per pixel designs utilizes 3 or 4 VETs per pixel and the amplifier consists of a source follower. The source follower is problematic in two-dimensional arrays due to threshold variations and resulting gain variations per pixel causing extensive peripheral circuitry and/or software to correct. The Active Column Sensor (ACS) employs a true Unity Gain Amplifier (UGA) per pixel, eliminating threshold and gain variations. The simplified pixel electronics allow for smaller and/or more sensitive pixels and always at lower cost through improved yields. Disclosure of 1 .5 FET double poiy, 1 .5 FET single poly, and photodiode configurations and with results on various pixels.

A CMOS video sensor for High Dynamic Range (HDR) imaging is discussed. Unlike traditional memoryintensive methods for HDR imaging where frames with different exposure times are digitally combined to obtain an HDR frame, HDR imaging is accomplished in the sensor at pixel level by digitally combining sub-pixels with different exposure times to obtain an HDR pixel. In HDR mode, the prototype video sensor demonstrated a phenomenal 26dB improvement in dynamic range over normal mode.

A new family of binary format CMOS CID imagers was designed to meet the random pixel addressing and on-chip signal manipulation requirements of many scientific applications. Key features include true random pixel and programmable subarray addressing, non-destructive readout and charge injection (clearing) that eliminate the need to read out superfluous pixels.And, programmable horizontal/vertical binning provides improved signal/noise and permits spatial signal consolidation even when reading out overlapping subarrays.The imagers incorporate on-chip preamplifiers for low noise readout.Inherent CID pixel characteristics such as non-destructive, non-blooming read-out that permit adaptive exposure control and linear dynamic range extension are maintained.Formats include 10242, 5122, and 1024 X 256. All incorporate 27.0 micron contiguous square pixels with in excess of i06 electron well capacity. Serial horizontal and vertical input ports are provided to accept the coordinates of the pixel or subarray to be readout. Rapid subarray readout is facilitated via a single pixel advance clock that is used in conjunction with each random access decoder. A description of the architecture, imager operation and application will be presented.