b) Figure 1. (a) Parity-check matrix H3⨉6, and (b) bipartite graph representation. 1 0 1 1 0 1 0 1 0 0 1 0 0 0 0 1 1 1 H = cn j bn i (a) (b) (c) Figure 2. (a) Base matrix, (b) QC sub-matrix representation with 1 on the lines and 0 otherwise, and (c) full-expanded QC parity-check matrix. S -1 0 S = = = 8 0 -1 12 4 -1 0 -1 e x p a n d i n g f a c t o r p = 16Abstract-This paper shows a triple-mode LDPC decoder design with two design techniques, the matrix reordering algorithm for multi-mode reconfiguration and the Single-Entry-Multiple-Data (SEMD) scheme for throughput enhancement. The matrix reordering algorithm can reduce the computational complexity from O(n!) to O(n 3 ). The SEMD can enhance the throughput by m times with small area overhead. With TSMC 0.13μm CMOS, the proposed design is synthesized in 1.99mm 2 area at 172.4MHz.

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