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A V-band variable gain amplifier (VGA) with wide gain control range, low phase variation, and low return loss variation is designed and implemented on 90-nm CMOS process. Utilizing a phase compensation capacitor at the common gate transistor and a source Figure 8 Simulated diversity, simulated realized gain, and measured realized gain against frequency 1946

This study proposes a method of designing a multiway power divider including all connecting lines. The multiway power divider is based on several interconnected two‐way power dividers. The connecting lines comprise the interconnecting sections, used for interconnecting the two‐way power dividers, and the input/output extension lines, used for connecting the internal circuit to the on‐board feeding ports. In the proposed method, the length of each interconnecting section can be flexibly partitioned to best fit the layout requirement. Every transmission line used for any purpose of connection in the layout is included as part of design and contributes to improvement of matching bandwidths. Therefore, a multiway power divider adopting the design method will result in better bandwidth performance for the same circuit size. The background principle of the proposed method and several simulated design scenarios are provided. A prototype of a four‐way power divider is designed and fabricated. The measurement results, decently matching the simulations, validate the proposed idea. This study for the first time discusses on design and optimisation of an entire multiway power divider including all portions of connecting lines. The proposed method can make a multiway power divider achieving an improved bandwidth and more efficient layout.

A Ku‐band 3‐bit switch‐type phase shifter with low insertion loss, low magnitude variation, and low rms phase error is designed and fabricated on 0.15‐μm pHEMT process. For all eight states, the insertion loss is 6.5 ± 1.5 dB from 10–14 GHz and the input return loss is >8.5 dB over 10–14 GHz. The phase shifter achieves a rms phase error of 2.2° and a rms amplitude error of 0.37 dB at 12 GHz with total chip size of 1.5 ×1 mm2. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:771–774, 2015