This manuscript proposes a way to tune fractional-order proportional-integral controllers, to synthesize them in hardware and to evaluate them by using hardware-in-the-loop technique. In order to validate the tuned controllers, it was imposed to control a plant where two loops of control were necessary. The obtained results showed satisfactory performance for both designed controllers and proved that fractional calculus can be implemented on high-performance digital processors. Controllers were implemented on the Altera DE2-115 cyclone IV EP4CE115 board.