In this paper, we implemented the conventional FAST and BRIEF algorithm as hardware on Zynq-7000 SoC Platform. Previous feature-based hardware accelerator is mostly implemented using the SIFT or SURF algorithm, but it requires excessive internal memory and hardware cost. The proposed FAST & BRIEF accelerator reduces approximately 57% of internal memory usage and 70% of hardware cost compared to the conventional SIFT or SURF accelerator, and it processes 0.17 pixel per clock.

As resolution for displays is recently more and more increasing, the amount of data and calculation that graphic hardware needs to process are also increasing. Especially the amount of data processing by Rasterizer is rapidly increasing. This paper used an algorism using coordinates in center of gravity and area for triangle instead of using bilinear algorism[1] used by conventional interpolation, which is to make it easier for parallel processing by Rasterizer. This paper implemented designed Rasterizer under FPGA environment and compared it with conventional Rasterizer and verified it. This Rasterizer is proved to have approximately 50% higher performance compared to conventional one.