No abstract

No abstract

A pseudo random access memory device which has an internal hierarchy of CCD shift register and MOS RAM on a same chip is proposed. The memory system structure using this device is analogous to the conventional cache-main memory system.Using a hardware simulator developped by the authors, performance of the memory system is simulated and the availability of this type of memory system is discussed.It is expected that the access time of the memory system can be very close to that of RAM part, and that the chip size of this type is slightly larger than usual CCD-SR, and approximately 4 times higher bit density than usual RAM may be attained. The memory system proposed here shows an attractive approach for realizing high speed large capacity main memory in the computer system.

No abstract

No abstract