Wireless communication exhibits the highest energy consumption in wireless sensor network (WSN) nodes. Due to their limited energy supply from batteries, the low power design have become inevitable part of today's wireless devices. Power has become a burning issue in VLSI design. In modern integrated circuits, the power consumed by clocking gradually takes a dominant part. Reducing the power consumption not only enhance battery life but also avoid overheating problem. By employing a more appropriate Processing Element (PE), the power consumption is significantly reduced. In this paper the novel method for low power design is achieved by using Folded

Multiplier and MAC is fundamental elements in DSP processors. Multiplication is one of the essential functions of arithmetic operation in computing systems, performing with different multipliers with different algorithms. MAC consisting of multiplier, adder and accumulator which plays a vital role in various DSP applications in improving signal processing ability, FIR and IIR filters. This article concentrates particularly on the efficient implementations of an accurate, signed and unsigned point multiplier. A modified booth Encoding (MBE) multiplier is used to execute a multiplier in floating point multiplier in order to significantly reduce partial products into half. CSA is applied with the inclusion of partial products in order into half. CSA is applied with the inclusion of partial products in order to improve speed.Rounding is not introduced to make the multiplier of a MAC unit more precise. Hence the proposed system shows an improved performance in systems area by 64.77%, reduced surplus power consumption by 44.41%, delay is reduced by 80% and shows a less circuit cost efficient. This proposed system area, power, delay, area delay product and power delay product are designed and calculated using synopsis, advanced VLSI tool.