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We propose a plasma and thermal damagefie gate process named "Dmnascerae gate process" where CMP (Chemical Mechanical Polishmg) is used in forming gate structure. By uSbg this process, M y planarized high performance metal (W/TiN or MiN) gate transistors with pure SiO, or TazO5 as gate insulators were fabricated with very d o r m and highly reliable electrical characteristics. Therdore, this technology is usehl in fabricating 0.1 pm MOSFETs and beyond.

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