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This paper presents the implementation of the first fully integrated pulse oximeter front-end with a power consumption lower than 1 mW. This is enabled by system- and block-level noise optimisation, also detailed in the manuscript. The proposed design features an analogue feedback loop that enables fast and accurate regulation of the detected photocurrent level and a serial-to-parallel interface allowing for extensive programmability of several operation parameters. The front-end was fabricated in the AMS 0.35 μm technology and occupies an area of 1.35 mm(2). Extensive measured results, both electrical and physiological from human subjects are reported, demonstrating an estimated SNR of 39 dB and ability to detect 2% changes in SpO2, similar to commercial pulse oximeters. This is despite the constrained power consumption which amounts to 0.31 mW for the LEDs and 0.53 mW for the rest of the front-end from a 3.3 V supply. Statistical results from 20 chips verify good matching across the Red and Infrared channels of the front-end and the accurate operation of the proposed analogue feedback loop.

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SUMMARY This paper advances the field of externally linear–internally nonlinear (ELIN) filters by introducing a synthesis method that enables the design of high‐order class‐AB sinh filters by means of complementary metal–oxide semiconductor (CMOS) weak‐inversion sinh integrators comprising only one type of devices in their translinear loops. The proposed transistor‐level synthesis approach is demonstrated through the examples of (1) a biquadratic and (2) a fifth‐order filter, and their simulated performance is studied. The biquadratic filter achieves a dynamic range of 94 dB and has a tunable quality factor Q up to the value of 8, whereas its natural frequency can be tuned for four orders of magnitude. Its static power consumption amounts to 6.2 μW for Q = 1 and fo = 2 kHz. The fifth‐order Chebyshev sinh CMOS filter with a cut‐off frequency of 100 Hz, a pass band ripple of 1 dB, and a power consumption of ~300 nW is compared head‐to‐head with its pseudo‐differential class‐AB CMOS log domain counterpart. The sinh filter achieves similar or better signal‐to‐noise ratio (SNR) and signal‐to‐noise‐plus‐distortion ratio (SNDR) performances with half the capacitor area but at the expense of higher power consumption from the same power supply level. All three presented filter topologies are novel. Cadence design framework simulations have been performed using the commercially available 0.35 µm AMS (austriamicrosystems) process parameters. Copyright © 2013 John Wiley & Sons, Ltd.