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For a capacitor formed of MOS device using Metal-silicon dioxide-silicon (MOS) layers with an oxide thickness of 528 Å (measured optically), some of the material parameters were found from the curve drawn between Capacitance vs Voltage (C-V) through the Visual Engineering Environment Programming (VEE Pro) software. To perform the measurment, process by a distance, from the hazardous room, we use VEE Pro software. In this research, to find good result, vary the voltage with smaller increments and perform the measurements by vary the applying voltage from +7V to-7V and then back to +7V again and then save this result in a Data sheet with respect to temperature, volage and frequency using this program.

To avoid the uses of multiple RF chain associated with the multiple antennas, RF switch is most essential component. Multiple antennas systems are used to replace traditional single antennas circuitry in the radio transceiver system in order to improve the transmission capability and reliability. The desired switching system must have low cost and simple structure, yet still can capture all the advantage of Multiple Inputs Multiple Output (MIMO) systems. In this paper, we have proposed a Double Pole Four Throw (DP4T) RF switch using Complementary Metal Oxide Semiconductor (CMOS) technology with inverter property. This switch is low in cost, and capable of selecting data streams to or from the two antennas for transmitting or receiving processes, respectively.

In this paper, we have explored the design features of a Double-Pole Four-Throw (DP4T) RF CMOS switch with use of a novel Vertical Slit Field Effect Transistor (VSFET). This proposed switch circuit uses the double-gate which minimizes the number of transistors and increases the logic density of the transistor per unit area as compare to simple switch. These double gates are independently controlled. This will provide a switch with a drive circuit that free from signal propagation delay and additional voltage power supply. Further, main objective is to provide a plurality of such switches arranged in a densely configured switch array, where the power and circuit area is reduced as compared to a tied gate configuration.