Traditionally, the advantages of compact image sensors (CISs) over CCDs have been low power consumption and the capability for system integration. Additionally, the image quality of CISs has recently begun to rival and even surpass that of CCDs in the area of high-speed imaging [1]. Compared to high-speed CCDs, CISs utilize the advantage of a column-parallel pixel readout. Column-parallel ADCs allow for low-bandwidth readouts. This is a key advantage over wide-bandwidth single-output amplifiers in CCDs or single ADC CISs. In order to realize these high-speeds, CISs need to simultaneously achieve a high-speed data rate and high image quality (equivalent to that of CCDs). A progressive 1/1.8-inch 1920×1440 CMOS image sensor with a column-inline dual-CDS architecture is designed in a 0.18µm CMOS process. This architecture implements high-speed digital sampling with analog CDS on column-parallel ADC for high-speed and highquality imaging. Random noise is 5.2erms at 180frames/s. The dynamic range at 180frames/s (corresponding to a 600MHz rate and 6.0Gb/s) is 68dB. The FPN is <0.5erms without the additional FPN-correction circuit.This CIS is composed of 6 main parts. 1) a 1920×1440 pixel array, 2) 1440 row decoders and drivers, 3) 1920 column parallel ADCs, 4) a single-slope ramp generator DAC with 12b accuracy, 5) digital logic control, and 6) a 12b LVDS interface (at a frequency of up to 600MHz). Figure 27.5.1 shows the block diagram of the whole system. The CIS operates with a single master clock at 74.25MHz. Additionally, a PLL generates a 297MHz clock, φ PLL , quadruple the master clock. This clock is supplied to the column ADCs, slope DAC, and the LVDS interface.• 2006 IEEE International Solid-State Circuits Conference 1-4244-0079-1/06 ©2006 IEEE

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