A silicon compiler for FIR filters is presented. Unlike existing silicon compilers for designing Digital Signal Processor (DSP) chips, which need descriptions for signal processing algorithms as inputs, the synthesis system takes as inputs only filter specifications and processing word lengths, and generates the FIR filter mask pattems in a few minutes. The system consists of two programs: an FIR filter design program to determine FIR filter coefficients at the minimal filter order to meet design objectives and a module generator to generate mask pattems, according to optimal parameters obtained by the filter design program. For describing layout structures correctly and easily, the module generator provides graphical layout description tools and includes mechanisms to permit designing the structures before leaf-cells are completed. Layouts for several filters have been successfully generated in a short time. A single chip VLSI chrominance/luminance separator for NTSC composite TV signals employing four FIR filters generated by the system is shown.

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