Inthis paper, we propose a code based technique, Variable-to-Fixed (V -F) coding, for power efficient test data compression. The proposed scheme with the aim of achieving high compression ratio and low power consumption relies on reducing, the number of bits for representing the original test vector and the number of transitions per second. Simulation results on ISCAS'89 benchmark circuits, demonstrate that this optimization methodology helps achieve reduced test data volume than previous schemes for cases where the number of specified bits in the test set is relatively few.

One of the major challenges in testing a system-on-a-chip (SoC