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We present critical-sink routing tree (CSRT) constructions which exploit available critical-path information to yield high-performance routing trees. Our CS-Steiner and "global slack removal" algorithms together modify traditional Steiner tree constructions to optimize signal delay at identified critical sinks. We further propose an iterative Elmore routing tree (ERT) construction which optimizes Elmore delay directly, as opposed to heuristically abstracting linear or Elmore delay as in previous approaches. Extensive timing simulations on industry IC and MCM interconnect parameters show that our methods yield trees that significantly improve (by averages of up to 67 %) over minimum Steiner routings in terms of delays to identified critical sinks. ERT's also serve as generic high-performance routing trees when no critical sink is specified: for 8-sink nets in standard IC (MCM) technology, we improve average sink delay by 19% (62%) and maximum sink delay by 22% (52%) over the minimum Steiner routing. These approaches provide simple, basic advances over existing performance-driven routing tree constructions. Our results are complemented by a detailed analysis of the accuracy andwelity of the Elmore delay approximation; we also exactly assess the suboptimality of our heuristic tree constructions. In achieving the latter result, we develop a new characterization of Elmore-optimal routing trees, as well as a decomposition theorem for optimal Steiner trees, which are of independent interest. I. INTRODUCTION UE to the scaling of VLSI technology, interconnection D delay has become a dominant concern in the design of complex, high-performance circuits [ 131, [34]. Performancedriven layout design has thus become an active area of research over the past several years. In this paper, we develop a new critical-sink problem formulation and new solutions for performance-driven routing tree design. For a given signal net, the typical goal of performancedriven routing is to minimize average or maximum sourcesink delay. Much early work implicitly equates optimal routing with minimum-cost Steiner routing. For example, [ 141 used static timing analysis to yield net priorities, so that Manuscript

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We present two critical-sink routing tree CSRT constructions which exploit critical-path information that becomes available during timing-driven layout. Our CS-Steiner heuristics with Global Slack Removal" modify traditional Steiner constructions and produce r outing trees with signi cantly lower criticalsink delays compared with existing performance-driven methods. We also propose a new class of Elmore routing tree ERT constructions, which iteratively add tree e dges to minimize Elmore delay. This direct optimization of Elmore delay yields trees that improve delays to identi ed critical sinks by up to 69 over minimum Steiner routings. ERTs also improve performance over such recent methods as 1 6 when no critical sinks are s p eci ed.