This work demonstrates the development of a 5-bit time to digital converter (TDC) using the local passive interpolation (LPI) technique. The TDC architecture achieves a high resolution, while maintaining a low conversion latency, and a good linearity over process variation at multi-GHz rate of operation, which simplifies the calibration process. The time-to-digital converter was fabricated in a 0.13 µm IBM CMOS process (CMRF8SF). At a sampling rate of 100 MHz the maximum frequency of operation was measured to be 1.6 GHz. The uncalibrated resolution of 8.1 psec and a dynamic range of 260 psec were measured. The TDC is compatible with loop counter architectures that can further extend its dynamic range. The raw integral (INL) and differential (DNL) non-linearity of 1.02LSB and 0.52LSB respectively were observed. A correlation with the simulated results confirmed that the proposed LPI-TDC can operate at 5 GHz with some adjustments to measurement setup, input matching, and the on-chip supply integrity. I am deeply grateful to all the people who in one way or another have supported me during my Masters of Applied Science thesis. This academic research has been an invaluable experience, which has embarked me on a path to continue exploring integrated ciruits in the future. In particular, I would like to acknowledge Professor John W.M. Rogers and Professor Calvin Plett at Carleton University for their technical assistance in the research and writing of this thesis. Their oversight and feedback has allowed me to grow immensly, both professionally and as a researcher. The valuable guidance has created a firm foundation for all my future endeavours. I would also like to extend a special thank you to Nagui Mikhail for ensuring the testing phase of my research went smoothly and that I had all the components and equipment required. To my family and friends, thank you for your encouragement and support during this process, without which, this undertaking would not have been possible.