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A hybrid delta-sigma/pipelined modulator is presented in this paper. The proposed modulator takes advantage of the high resolution and distributed pipelined quantization, and combines it with the noise shaping property of a delta-sigma modulator. As a result, gain, swing, and slew requirements of the integrators are significantly reduced. The modulator also makes use of the latency in the pipelined quantization to enhance noise shaping. These advantages lead to less power dissipation, increased stability, and higher resolution. The prototype chip is implemented in a 0.18 m CMOS process. With an 80 MHz clock, and an oversampling ratio of 8 (5 MHz bandwidth), the measured dynamic range and SNDR of this prototype IC are 79 dB and 75.4 dB.

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