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Power supply noise induced jitter (PSIJ) is one of the critical bottlenecks for I/O signal performance. Good power distribution network (PDN) is a must for high-end system designs. Due to design limitation in die and package, providing sufficient on-die capacitor (ODC) or on-package capacitor (OPD) is a very challenging task. This paper presents a novel on-die decoupling scheme which places decoupling caps in core area and connects to I/O area by package interconnects. The presented method is applied to DDR interface in med-end FPGA devices. Excellent SSN improvement is achieved by implementing this scheme.

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