No abstract

No abstract

Abstract-This paper describes the design of a highperformance unified SVM classifier circuit. The proposed circuit supports both linear and non-linear SVM classifications. In order to ensure efficient classification, a 48x96 or 64x64 sliding window with 20 window strides is used. We reduced the circuit size by sharing most of the resources required for both types of classification. We described the proposed unified SVM classifier circuit using the Verilog HDL and synthesized the gate-level circuit using 65nm standard cell library. The synthesized circuit consists of 661,261 gates, operates at the maximum operating frequency of 152 MHz and processes up to 33.8 640x480 image frames per second.

Transfer Level) and synthesized into a gate-level circuit using 130nm standard cell library. The resultant circuit This paper presents a new method to design the circuit that includes 69,928 logic gates and its maximum operating can perform the inverse transform and inverse quantization frequency is 123.1MHz. operations for three popular video compression standards WMV9, MPEG-4 and H.264. We introduced a delta 2. BACKGROUND coefficient matrix and implemented the integrated inverse transform circuit based on the proposed idea. We designed The IDCT of WMV9 is defined as the following matrix the integrated inverse quantization circuit using a shared equations: multiplier. The entire circuit was verified on the SoC platform board, synthesized into a gate-level circuit using EMXN= (XMXN WNXN+ 4) >>3 130nm standard cell library and showed its efficiency in RmN (WT £m+ C 1 1-4244-1222-6/07/$25.00 ©)2007 IEEE

No abstract