Abstract-In this paper, a 320 × 240 pixel, 80 frame/s CMOS image sensor with a low power dual correlated double sampling (CDS) scheme is presented. A novel 8-bit hold-and-go counter in each column is proposed to obtain 10-bit resolution. Furthermore, dual CDS and a configurable counter scheme are also discussed to realize efficient power reduction. With these techniques, the digital counter consumes at least 43% and at most 61% less power compared with the column-counters type, and the frame rate is approximately 40% faster than the double memory type due to a partial pipeline structure without additional memories. The prototype sensor was fabricated in a Samsung 0.13 µm 1P4M CMOS process and used a 4T APS with a pixel pitch of 2.25 µm. The measured column fixed pattern noise (FPN) is 0.10 LSB.

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