This work presents the large area fabrication of plasmonic colour filters consisting of subwavelength apertures in aluminium films of different thicknesses. Wafer-scale pattern transfer was realized by a soft lithography technique (substrate conformal imprint lithography). The fabricated colour filters have an active area of up to 145 cm2 which presents a considerable increase compared to previously published results. In addition to experimental investigations, simulations of the transmission behaviour were performed using a rigorous electromagnetic field solver based on an extended RCWA approach. Furthermore, the use of a spin-coated cover layer consisting of the UV-curable hybrid polymer OrmoComp® instead of often applied PECVD-SiO2 was investigated.

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This study addresses the complementary metal-oxide-semiconductor (CMOS)-compatible fabrication of vertically stacked Si/SiO2/Si nanopillars with embedded Si nanodots as key functional elements of a quantum-dot-based, gate-all-around single-electron transistor (SET) operating at room temperature. The main geometrical parameters of the nanopillars and nanodots were deduced from SET device simulations using the nextnano++ program package. The basic concept for single silicon nanodot formation within a confined oxide volume was deduced from Monte-Carlo simulations of ion-beam mixing and SiOx phase separation. A process flow was developed and experimentally implemented by combining bottom-up (Si nanodot self-assembly) and top-down (ion-beam mixing, electron-beam lithography, reactive ion etching) technologies, fully satisfying process requirements of future 3D device architectures. The theoretically predicted self-assembly of a single Si nanodot via phase separation within a confined SiOx disc of < 500 nm³ volume was experimentally validated. This work describes in detail the optimization of conditions required for nanopillar/ nanodot formation, such as the oxide thickness, energy and fluence of ion-beam mixing, thermal budget for phase separation and parameters of reactive ion beam etching. Low-temperature plasma oxidation was used to further reduce nanopillar diameter and for gate oxide fabrication whilst preserving the pre-existing nanodots. The influence of critical dimension variability on the SET functionality and options to reduce such deviations are discussed. We finally demonstrate the reliable formation of Si quantum dots with diameters of less than 3 nm in the oxide layer of a stacked Si/SiO2/Si nanopillar of 10 nm diameter, with tunnelling distances of about 1 nm between the Si nanodot and the neighboured Si regions forming drain and source of the single-electron transistor.