Since 2001 the IEEE P1581 working group aims to provide a test standard for memories that cannot have boundary scan. Currently this P1581 activity focuses on test access and test circuitry. This paper will elaborate on the status of the draj? standard. It describes the test circuitry and an economic model for users of P1581 devices ispresented. The working group is facing a lack of interest of active participants. Continuation of the P1581 standard is currently under discussion. An introduction to a discussion for the future of P1581 is

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