A single integer h e a r programming model for optimally scheduling partitioned regular algorithms is presented. The herein presented methodology differs from existing methods in the following capabilities: 1) Not only constraints on the number of uvailable processors and communication capabilities are taken into account, but also processor caches and constraints on the size of available memories are modeled and taken into account in the optimization model. 2) Diferent types of processors can be handled.3) The size of the optimization model (number of integer variables) is independent of the size of ihe tiles to be executed. Hence, 4) the number of integer variables in the optimization moder' is greatly reduced suchthat problems of relevant size can be solved in practical execution time. 1: IntroductionThis paper deals with techniques for mapping partitioned regular algorithms onto massively parallel processor arrays that are realized in VLSI.The most important problems to be solved in the synthesis process include scheduling where the operations in the algorithmic description are mapped onto discrete time steps, and binding where the operations and variables in the algorithmic description are mapped onto shared hardware resources.Partitioning methods have been proposed for mapping an arbitrary size regular algorithm onto a processor array with a restricted number of processing elcments and dimension. The aim is to establish a balance between local memory, I/O-rate and computation rate, see e.g., [20, 151. However, while the emphasis of partitioning has generally been on restricted resources on the array level (i.e., number of processing elements) (regular resource constraints), typical problems like a constrained number of functional resources, communication resources and memory resources inside the processing elements (so called irregukrr refource constraints) have been ignored. For example, the number of available function units in a processing element is not sufficient to execute the operations assigned to them concurrently.As a result, a new research direction on extending array mapping methodologies can be recognized in the fusion of mapping techniques for regular processor arrays and high-level synthesis tasks, see, e.g., [20, 4, 2, 18, 6, 51. Here is a short overview of recent work in this direction:Except of special cases, resource constrained scheduling problems are known to he NPcomplete, see e.g., [3, 71. Hence, numerous heuristic methods have been proposed in order to

A b s t r a c t -S e l l i n g and purchasing power are important activities for utilities because of potential savings.When a selling utility presents a n 'offer including prices, power levels a n d durations, a purchasing utility selects power levels and durations within the offered range subject to relevant constraints.The decisionmaking process i s complicated because transactions are coupled with system demand and reserve, therefore decisions have to be made In conjunction with the commitment and dispatching of units.Furthermore, transaction decisions have to be made in almost real time in view of the competitiveness of the power market caused by deregulation.In this paper, t r a n s a c t i o n s are analyzed from a selling utility's viewpafnt for a system consisting of thermal, hydro and pumpedstorage units.To effectively solve the problem, linear sale revenues are approximated by nonlinear functions, and non-profitable options are Identified and eliminated from consideration.The multipliers are then updated a t the high level by using a modified subgradient method to obtain near optimal solutions quickly.Testing results show that the algorithm produces good sale offers efficiently.