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In this paper, the design of a low-cost ultra-high-frequency (UHF) Radio Frequency IDentification (RFID) tag chip with an advanced encryption standard (AES) cryptographic engine is presented. The design of digital baseband is verified on a Field-Programmable Gate Array (FPGA) platform. The whole chip, including a radio frequency frontend, an analog frontend, an Electrically Erasable Programmable Read-Only Memory (EEPROM), and a baseband with AES engine, is taped out on Semiconductor Manufacturing International Corporation (SMIC) 0.13mm process. The chip area is 1 Â 1 mm2, in which 0.6 Â 0.3 mm2 is covered by the digital baseband. The power consumption of the entire tag chip is 20.9 mW. The design can work on both two modes of the standard ISO 18000-6C mode and the security enhanced ISO 18000-6C mode. To the best of our knowledge, it is the first UHF passive RFID tag chip with AES algorithm in the baseband.

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