Multilevel medium voltage inverters have become an important technology in the power electronics industry to drive high-power motors.Since these converters are typically operated at very low switching frequencies, the use of modulation based on predefined switching patterns such as Synchronous Optimal Pulse Width Modulation (SOP) is advantageous. However, digital realization of this kind of modulator poses a challenge since the typical digital signal processors do not have a direct way to implement this type of modulation, and real-time modulator reconfiguration is typically used whenever the control strategy needs to change the count of switching per cycle of the fundamental. When implemented via software this leads to possible discontinuities in the process, imposes additional time restrictions and has the potential to cause currents and torque disturbances. This work presents a novel solution for the digital implementation of such a modulator based on multilevel waveform pattern decomposition that can handle switching patterns with different counts of switching per cycle in a single modulation structure, without requiring any dynamic reconfiguration. This, in addition to a hardware-based approach through an FPGA device, provide a modulation with very low harmonic distortion and seamless transitions when the number of switching per cycle is changed. The proposal is tested on an experimental setup of a 5-level NPC Hbridge (HNPC) inverter driving a Permanent Magnet Synchronous Machine (PMSM).