The concept of a SOC platform architecture introduces the concept of a communication infrastructure. In the transaction-level a finite set of architecture components (memories, arithmetic units, address generators, caches, etc)

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Bus performances are extremely important in a platform-based design. System Level analysis of bus performances gives important information for the analysis and choice between different architectures driven by functional, timing and power constraints of the System-on-Chip. This paper presents the effect of different arbitration algorithms and bus usage methodologies on the bus AMBA AHB performances in terms of effective throughput and power dissipation. SystemC and VHDL models have been developed and simulations have been performed.

High level design methodologies are needed to overcome the complexity of System on Chip design. In this paper the SystemC environment has been used to design a Bluetooth transceiver. The high simulation speed allowed a high level performance analysis of the IP developed and the definition of an algorithm for selecting the best packet type in presence of channel noise.

The paper presents a new model of the dynamic power dissipated by a circuit described at gate or behavioural level.A procedure is presented for an accurate estimate of the power dissipated during the execution of each instruction by using gate level or behavioural level digital simulations. The information on power consumption stored in a Look-up Table can be used in a System level simulation. The methodology has been applied to the design of an 12C bus driver.