DPLAYOUT is a layout synthesis tool for bit-sliced datapath designs targeting standard-cell libraries. We developed fast and e c i e n t heuristics for placing the cells in a bit-slice, such that the regulariv of datapath circuits is preserved and the number of channels occupied by a control signal is minimized. In addition, we propose a novel window-based heuristic for global routing of multipin nets. VHDL interface makes DPLAYOUT a general tool which can be easily integrated with any high-level synthesis system. This paper describes the heuristics developed for placement and global routing of a single bit-slice. We compared the area and run-time efficiency of the proposed heuristics with conventional methods and the results show a significant improvement.