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A dual-core baseband processor IC for GSM/GPRS cellular phone applications is built in a 0.13pn CMOS process with 5 levels of copper interconnect and contains a high level of mixed-signal integration which includes: 1GHz CMOS synthesizer, 10b general-purpose ADC, two 14b ADCs, power amplifier controller, and 13b voice CODEC. k D. Redmond

This paper describes a multi component mixed process "System-in-a-Package" (SIP) transceiver suitable for wireless quad band EGPRS applications. The unique approach of pursuing this SIP enables faster time to market, mitigates risk and reduces customer's development cycle time. This solution offers antennae-to-bits functionality using less than 250mm 2 of valuable board space. The Tx and Rx performance results are shown and the technology developed to implement the transceiver solution is described. The module integrates three IC's; 0.18µm RF-CMOS for RF/Analog, 0.13µm CMOS for Mixed Signal Analog/Digital/DSP and GaAs for Integrated Passive Devices (IPD). It contains a Quad Band Balun plus surface mount devices (SMD) for loop filter and RF bypass. It has the complete transmit line up from digital bits (as per DigRF standard [1]) to power amplifier interface, as well as receive function from LNA inputs to bits (per DigRF standard).

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