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An user programable high-speed fixed point digital signal processor (DSP) has been developed. 50ns machine cycle has been achieved by adopting the following three new techniques: (1) originally designed DSI' architecture, ( 2 ) no overflow halt high-speed ALU and (3) short access time clocked EPROM. The chip has been fabricated by 1 . 2~ m standard CMOS process without additional process such as polyside. 6.4.1 IEEE 1992 CUSTOM INTEGRATED CIRCUITS CONFERENCE0-7803-0246-xI92 $3.00 1992 IEEE

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