-Using the exibility provided by multiple functionalities we have developed a new approach for permanent fault-tolerance: Heterogeneous BuiltIn-Resiliency (HBIR). HBIR processor synthesis imposes several unique tasks on the synthesis process: (i) latency determination targeting k-unit fault-tolerance, (ii) application-to-faulty-unit matching and (iii) HBIR scheduling and assignment algorithms. We address each of them and demonstrate the eectiveness of the overall approach, the synthesis algorithms, and software implementations on a number of designs.

Numerous fast algorithms for the Discrete Cosine Transform (DCT) have been proposed. Until recently, it has been difficult to compare different DCT algorithms and select one which is best suited for implementation under a given set of design goals. We propose an approach for design space exploration at the algorithm and behavioral levels using behavioral synthesis tools and demonstrate its effectiveness for designing DCT ASIC. In particular, we study and compare the following nine DCT algorithms: Lee's, Wang's, DIT, DFT, Arai's, DIF, Vetterli's, planar rotation, and direct algorithm. The main conclusions of this study are (i) the best choice among fast DCT algorithms depends on a particular set of design goals and constraints and (ii) almost always more than an order of magnitude improvement can be achieved using algorithm and behavioral design space exploration.

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